
--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   15:50:57 01/19/2011
-- Design Name:   COPROCESSOR
-- Module Name:   /tp2/xima3s/xima3s23/Desktop/copro_final/vhdl//tb_coprocessor_irq.vhd
-- Project Name:  coprocessor
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: COPROCESSOR
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
USE work.CONSTANTS.ALL;

ENTITY tb_coprocessor_irq_vhd IS
END tb_coprocessor_irq_vhd;

ARCHITECTURE behavior OF tb_coprocessor_irq_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT COPROCESSOR
	PORT(
		clk : IN std_logic;
		rst : IN std_logic;
		data_in : IN std_logic_vector(31 downto 0);
		addr : IN std_logic_vector(12 downto 0);
		rd_en : IN std_logic;
		wr_en : IN std_logic;          
		data_out : OUT std_logic_vector(31 downto 0);
		req_irq : OUT std_logic
		);
	END COMPONENT;

	--Inputs
	SIGNAL clk :  std_logic := '0';
	SIGNAL rst :  std_logic := '0';
	SIGNAL rd_en :  std_logic := '0';
	SIGNAL wr_en :  std_logic := '0';
	SIGNAL data_in :  std_logic_vector(31 downto 0) := (others=>'0');
	SIGNAL addr :  std_logic_vector(12 downto 0) := (others=>'0');

	--Outputs
	SIGNAL data_out :  std_logic_vector(31 downto 0);
	SIGNAL req_irq :  std_logic;
	
	constant clk_period : time := 1 ns;
BEGIN
	-- Instantiate the Unit Under Test (UUT)
	uut: COPROCESSOR PORT MAP(
		clk => clk,
		rst => rst,
		data_in => data_in,
		addr => addr,
		rd_en => rd_en,
		wr_en => wr_en,
		data_out => data_out,
		req_irq => req_irq
	);
	
	clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;

	stim_proc: process
   begin		
      wait for clk_period*1.5;	
	rst <= '0';
      wait for clk_period;
	  
	  -- reset address
	  rd_en <= '0';
	  wr_en <= '0';
	  addr <= (others => '0');
	  wait for clk_period;

	  -- Set Monitoring Length
	  wr_en <= '1';
      data_in <= X"0000001B";
	  addr(MON_LEN_ADDR) <= '1';
	  wait for clk_period;
	  addr <= (others => '0');
	  wr_en <= '0';
	  wait for clk_period;

	  -- set scan period
	  wr_en <= '1';
      data_in <= X"00000100";
	  addr(SCAN_PERIOD_ADDR) <= '1';
	  wait for clk_period;
	  addr <= (others => '0');
	  wr_en <= '0';
	  wait for clk_period;
	  
	  -- set Configuration String
	  wr_en <= '1';
      data_in <= X"00000005";
	  addr(CONFIG_BUFFER_BASE_ADDR) <= '1';
	  wait for clk_period;
	  addr <= (others => '0');
	  wr_en <= '0';
	  wait for clk_period;
	  
	  -- set Configuration String
	  wr_en <= '1';
      data_in <= X"76543210";
	  addr(CONFIG_BUFFER_BASE_ADDR+1) <= '1';
	  wait for clk_period;
	  addr <= (others => '0');
	  wr_en <= '0';
	  wait for clk_period;

	  -- set Configuration String
	  wr_en <= '1';
      data_in <= X"FEDCBA98";
	  addr(CONFIG_BUFFER_BASE_ADDR+2) <= '1';
	  wait for clk_period;
	  addr <= (others => '0');
	  wr_en <= '0';
	  wait for clk_period;
	  
	  -- set Configuration String
	  wr_en <= '1';
      data_in <= X"12345678";
	  addr(CONFIG_BUFFER_BASE_ADDR+3) <= '1';
	  wait for clk_period;
	  addr <= (others => '0');
	  wr_en <= '0';
	  wait for clk_period;
	  
	  -- start monitoring	  
      data_in <= CMD_START;
	  addr(CMD_ADDR) <= '1';
	  wr_en <= '1';
	  wait for clk_period;
	  addr <= (others => '0');
	  wr_en <= '0';
	  wait for clk_period;
	  
      data_in <= CMD_NOP;
	  addr(CMD_ADDR) <= '1';
	  wr_en <= '1';
	  wait for clk_period;
	  addr <= (others => '0');
	  wr_en <= '0';
      
		wait for 100*clk_period;
		-- Acknowledge irq
	  addr(IRQ_ADDR) <= '1';
	  rd_en <= '1';
	  wr_en <= '0';
	  wait for clk_period; -- read irq
	  rd_en <= '0';
	  wr_en <='1';
	  addr(IRQ_ADDR) <= '1';
	  data_in <= X"00000000";
	  wait for clk_period; -- write 0 in irq reg
	  addr <= (others => '0');
	  wr_en <= '0';
	  rd_en <= '0';
		wait for 80*clk_period;
		
		-- Acknowledge irq
	  wait for 120*clk_period;
	  addr(IRQ_ADDR) <= '1';
	  rd_en <= '1';
	  wr_en <= '0';
	  wait for clk_period; -- read irq
	  rd_en <= '0';
	  wr_en <='1';
	  addr(IRQ_ADDR) <= '1';
	  data_in <= X"00000000";
	  wait for clk_period; -- write 0 in irq reg
	  addr <= (others => '0');
	  wr_en <= '0';
	  rd_en <= '0';
	  
	  wait;
	END PROCESS;

END;
